| Urgent Hiring || ASIC Emulation Engineer || 100% Remote || , at Remote, Remote, USA |
| Email: [email protected] |
|
http://bit.ly/4ey8w48 https://jobs.nvoids.com/job_details.jsp?id=1033153&uid= From: Steve, GVD SYSTEMS LLC [email protected] Reply to: [email protected] Title: ASIC Emulation Engineer Location: 100% Remote Duration: 6 months Interview: Skype/Phone Must have skills: Cadence Palladium and/or Synopsys Zebu and. or Veloce **NOTE: Before you screen them confirm that they have not already applied to this client Key Responsibilities: Responsible for emulation infrastructure, compile and runtime execution of tests on industry standard emulation platform, preferably Cadence Palladium Enable and validate PCIe interface (such as Cadence Speed Bridge), associated host software and other externally connected IO devices such as I2C, SPI, UART, SM, JTAG and GPIO. Work effectively with ASIC, firmware and software teams to enable and run test suites. Develop automation on the emulation platform for end-to-end build and run methodology, perform debug and root cause failures efficiently. Train and support RTL and DV teams on emulation methodology Minimum Qualifications: 8+ years experience in ASIC design, verification, and emulation, tape outs of complex high performance SOCs 4+ years hands-on experience with leading emulation platforms, preferably on Cadence Palladium Exposure to design and design verification using System Verilog and UVM Debug experience in a HW/SW co-design environment Solid automation skills and familiarity with scripting (TCL, Python, Perl, -scripting) Title: ASIC Emulation Engineer Location: 100% Remote Duration: 6 months Interview: Skype/Phone Must have skills: Cadence Palladium and/or Synopsys Zebu and. or Veloce **NOTE: Before you screen them confirm that they have not already applied to this client Key Responsibilities: Responsible for emulation infrastructure, compile and runtime execution of tests on industry standard emulation platform, preferably Cadence Palladium Enable and validate PCIe interface (such as Cadence Speed Bridge), associated host software and other externally connected IO devices such as I2C, SPI, UART, SM, JTAG and GPIO. Work effectively with ASIC, firmware and software teams to enable and run test suites. Develop automation on the emulation platform for end-to-end build and run methodology, perform debug and root cause failures efficiently. Train and support RTL and DV teams on emulation methodology Minimum Qualifications: 8+ years experience in ASIC design, verification, and emulation, tape outs of complex high performance SOCs 4+ years hands-on experience with leading emulation platforms, preferably on Cadence Palladium Exposure to design and design verification using System Verilog and UVM Debug experience in a HW/SW co-design environment Solid automation skills and familiarity with scripting (TCL, Python, Perl, -scripting) Keywords: card Colorado http://bit.ly/4ey8w48 https://jobs.nvoids.com/job_details.jsp?id=1033153&uid= |
| [email protected] View All |
| 11:00 PM 19-Jan-24 |