| RTL/ASIC DESIGN :; Santa Clara - 3 days onsite is preferred :: Rate: - More than Expectation at Remote, Remote, USA |
| Email: [email protected] |
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http://bit.ly/4ey8w48 https://jobs.nvoids.com/job_details.jsp?id=1163704&uid= Oorwin Email RTL/ASIC DESIGN Location: - Santa Clara - 3 days onsite is preferred Experience: - 4+ Rate: - More than Expectation JOB DUTIES: The work will expose the designer to a number of IP including ARM cores, Ethernet, DDR, DMA, PCIE, SATA and AMD internal IPs. Successful candidates will be responsible for leading, and participating in, the design of leading edge SoCs in advanced digital CMOS processes. Our RTL Design Engineers are expected contribute in all aspects of SoC design including: Chip definition, Architecture development and modeling, Development of micro-architectural specifications, Conversion of micro-architectural specifications to logic implementation, Verification, emulation, debug, synthesis, and timing closure, Interfacing with physical execution, software, and silicon bring-up teams. EXPERIENCE AND EDUCATION: - SoC Architecture; - Knowledge AND hand-on experience from industry ASIC design flow including RTL coding, IP Integration, debugging/verification, and supporting synthesis and timing closure. - Working knowledge of ARM cores and other I/O standard interfaces. Best Regards, Sandeep Parida Team Lead Direct: 216-435-6693 Email: [email protected] Enfycon Inc. 6500 Emerland Parkway,Suite-100 Dublin, Ohio-43016 www.enfycon.com Keywords: http://bit.ly/4ey8w48 https://jobs.nvoids.com/job_details.jsp?id=1163704&uid= |
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| 03:33 AM 28-Feb-24 |