| Need Consultant for Design Verification Engineer - Capgemini - Santa Clara ,CA - Onsite at Santa Clara, California, USA |
| Email: [email protected] |
| Hi, Hope you are doing Good. This is Santhoshi from HAN IT Staffing. Today we have a requirement for the Design Verification Engineer position with the client Capgemini - Santa Clara ,CA - Onsite Do you have any consultants regarding this position Please share with me the resume of your consultant : [email protected] Role : Design Verification Engineer Implementation partner : Capgemini Location : Santa Clara ,CA Role: Design Verification Engineer - Onsite Client Name capgemini Work Location: Santa Clara ,CA JOB DESCRIPTION: Responsibility: write and debug UVM and System verilog tests at RTL and gate level for optical communication designs with SPI,I2C,AHB,APB interfaces and VIP driving them Experience : ~ 10 years of DV experience Skills: UVM/System verilog, cadence tools, VCS tools, using and integrating VIP, above mentioned protocols experience , GLS bring up and debug and other standard DV experience of creating TB and testcase. Good to have some real number modeling of analog designs in SystemVerilog, not mandatory. UVM/System verilog, cadence tools, VCS tools, using and integrating VIP, above mentioned protocols experience , GLS bring up and debug and other standard DV experience of creating TB and testcase. Good to have some real number modeling of analog designs in SystemVerilog, not mandatory. Global Grade = C / Electrical Engineer - Experience = Seven to Ten Years Electrical Engineer - Proficiency in Experienced Electrical Engineer - How Recent in Less than 3 Years -- Santhoshi Bangari, US IT Recruiter HAN IT Staffing Inc. (606) 252-1779 (C) [email protected] www.hanstaffing.com 33 Wood Ave South, Ste. 715 Iselin, NJ 08830 Keywords: cprogramm information technology California New Jersey |
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| Tue Mar 05 00:55:00 UTC 2024 |