| #Urgent- Pre-Silicon Verification Engineer- San Jose, CA at San Jose, California, USA |
| Email: [email protected] |
| From: Adithya Rangaraju, kksoftware associates [email protected] Reply to: [email protected] Hi, Greetings from KK Software Associates. This is Adithya. R from KK Software Associates. I have an urgent requirement of Pre-Silicon Verification Engineer, please go through the below requirement and forward me your updated resume with contact details ASAP. Title: Pre-Silicon Verification Engineer Location: San Jose, CA Duration: 12+Months Experience: 8-10 Note: Please do not submit OPT, CPT & H4 Job Description: Write verification specifications, verification plans, and documentation. Develop test benches and automate regression plans. Understand the specifications, use cases and develop System Verilog and C based testbenches in UVM environment and assertions. Develop make files, Python, and Perl scripts to automate the verification tasks. Perform complete block-level verification and contribute to the SOC chip level verification. Be responsible for complete verifications, simulations, and debugging of verification testbenches. Interface with cross-functional teams to understand the use cases and collaborate in all the SOC verification related activities. Requirements/Qualifications BS/MS in Electrical or Computer Engineering, 0 to 2 years of relevant work experience. Experience with System Verilog and Assertions. Experience with Verification and UVM. Exposure to FPGA design flows. Percentage of Shift and Longest Time. Review/Documentation/Test planning/Meetings: 15% Environment creation/test development: 40% Debug, Analysis, Coverage Closure: 45% Keywords: cprogramm rlang golang microsoft California |
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| Tue Mar 05 02:08:00 UTC 2024 |