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JOB | Hardware Design Engineer | Hybrid CA at Remote, Remote, USA
Email: [email protected]
From:

Manoj Rathee,

Sunray Enterprise, Inc.

[email protected]

Reply to:   [email protected]

Hi
Dear
,

I hope my mail finds you in good health and doing well!

We currently have the JOB POSITION listed below available.

Kindly go through the job description and share your latest updated RESUME, visa copy, and photo ID so that I can submit the profile to the client

.

Job Position         :-            Hardware Design Engineer

Locations             :-           
HYBRID, Mountain View, California

Duration                :-             Long Term

Job Description:-

Skills Required:

Years of Experience Required:
10+ overall years of experience in the field.

Degrees or certifications required:
Looking for actual experience degree is less important, however a Bachelors degree in Electrical Engineering, Computer Engineering, Computer Science, or related degree would be relevant.

Disqualifiers: Candidates with history of short-term contracts /
job hopping will not be eligible for the role.

Best vs. Average: The ideal resume would contain
someone who has worked for Microsoft before and has UVM skillset. Projects are less important to the sponsor as technical skills are needed.

Responsibilities:

Define, document, and implement a UVM verification environment including agents and scoreboards

Write test plans and implement them by developing tests, test generators, test benches, checkers, coverage, and other verification collateral

Run tests on RTL and Gate Level Netlists, debug failures to root cause, and recommend fixes

Support post-silicon verification activities of the products working with design and product teams

Top 3 Hard Skills Required

Proficient in
defining and developing unit and IP/SoC level test benches using SystemVerilog and VMM/OVM/UVM (5+ YOE)

Experience with
high Speed Serial or wide parallel interfaces such as D2D, Ethernet/PCIe/USB or DDDR PHY IPs (5+ YOE)

Analog and Mixed-signal IP's such as ADC's, Bandgaps, Power Regulators (5+ YOE)

Run tests on RTL and Gate Level Netlists, debug failures to root cause, and recommend fixes (5+ YOE)

Hope to hear from you soon !!!

Keywords: golang Idaho
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Thu Mar 14 20:16:00 UTC 2024

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