| Soc integration engineer-CA at San Jose, California, USA |
| Email: [email protected] |
| From: sravani, nitya INC [email protected] Reply to: [email protected] Location: San Jose, CA or willing to relocate. Soc integration engineer Need some help here. Attached is a great profile example of someone that we need to find ASAP. Similar to an RTL Design Engineer req you may have seen in the past. More of an L2 (3-7 years exp). The ideal candidate can help along our design flow to establish synthesis runs with the related timing constraints, perform Lint, CDC, DFT checks, support regression and release process and analyze STA timing results. Set of expertise: Able to read and understand SystemVerilog/Verilog RTL source code Proficient with Synopsys DesignCompiler and/or Design Compiler Ultra Proficient to work with TSMC Synthesis Libraries and Memory Macro generation Proficient with STA and PrimeTime and related timing constraints methodology and SDC constraints language Able to run RTL and 3rd party IP RTL through Lint, CDC check, DFT check with Spyglass or VC Static and generate clean reports Able to write python, tcl and other typical scripting languages Able to swiftly debug flow and tool errors Familiar with yaml is a plus Familiar with setting up and debugging GLS runs Familiar with bug tracking systems like Jira Familiar with revision control systems like Git Good written communication skills Self-motivated and efficient Keywords: California |
| [email protected] View all |
| Thu Mar 21 21:52:00 UTC 2024 |