| Design Verification Engineer with UVM in Pleasanton CA or Austin, TX Contract W2 C2C Onsite from day one at Austin, Texas, USA |
| Email: [email protected] |
| From: koshal arora, Tanisha Systems [email protected] Reply to: [email protected] Hi, Hope you are doing good! Design Verification Engineer Pleasanton CA or Austin, TX(Onsite only) Contract W2/C2C Job Description: Responsible for developing pre-silicon functional verification solutions for our cutting edge cellular IoT family of products The responsibilities of this role also include : Derive test plan from architectural requirements and design documents. Execute the verification strategies of SoC, and IP cores. Create test testbench architecture, develop reference models, bus-functional models and drivers to verify the design requirements. Integrate Verification IPs from different vendors. Developing tests and tuning the environment to achieve coverage goals. Own and debug failures in simulation to root cause problems Analysis and closure of code and functional coverage. Key Qualifications: Advanced knowledge of HVL methodology like UVM. Proven track record of full SOC cycle from concept to tape-out to bring-up. Experience in taping out large SOC systems with embedded ARM processor cores. Hands-on verification experience of AXI Bus Fabric, APB, AHB, and AXI, based bus architecture in UVM environment. Create IP level module and sub-system verification plan, reusable Test Benches, test sequences, test infrastructure. Create UVM based coverage driven verification plans from design specifications, review and refine to achieve coverage targets. In-depth knowledge and experience of working with low power design, UPF integration, boot sequence, power cycle, HW/SW interaction verification. Knowledge of ARM low power design and power policy unit. Understand the details of High Efficient High performance SOC Architecture, standard SOC component like Timer, DMA, memory management schemes, low power spec, multi-processor systems, Memory Controller Sub Systems, PLL, power up and Secured Boot schemes. Working knowledge of basic IO protocols (SPI/Octal SPI/I2C/UART/I2S/I3C) High speed I/O protocols such as Ethernet, SDIO, USB2.0, MIPI DSI/CSI Work closely with DV leads to improve verification flow. Strong experience with scripting languages like Perl and Python Should be a great teammate with excellent communication and problem-solving skills and the desire to seek diverse challenges. BSEE or MSEE with 7+ years of dedicated/hands-on DV experience using System Verilog Koshal Arora Account Manager Tanisha Systems Inc Phone:212-729-6543 Ext 393 Email:[email protected] Address:99 Wood Ave South Suite # 308 Iselin, NJ 08830 www.tanishasystems.com |
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| Wed Nov 09 14:33:00 UTC 2022 |