| Design Verification Engineer at Remote, Remote, USA |
| Email: [email protected] |
| From: Santhoshi, HAN IT Staffing [email protected] Reply to: [email protected] Role : Design Verification Engineer - Onsite Location: AUSTIN (US:73301), TX Client : Capgemini Job Description : o Defining and writing IP verification plans based on requirements documents (industry standards, product requirements, IP architecture and IP implementation specifications) o Writing stimulus in System Verilog (UVM), random test scenarios, algorithmic and directed testcases. o Defining and writing System Verilog Assertion (SVA) cover properties to match the verification plan. o Writing System Verilog (UVM) monitors, drivers, response checkers and SVAs for correctness. o Debugging failing testcases to determine source of failure (tool, testcase, checker, Verilog RTL) and track resolution o Collecting code and functional coverage results from random simulations, and analyzing uncovered events to determine additional test scenarios needed to achieve 100% coverage. Verilog, System Verilog, UVM Job Qualifications: o Verilog, System Verilog, UVM coding skills required. o Verification skills (test planning, testcase, testbench, simulation, debug) required. o Knowledge of ARM AMBA protocols a plus. o Knowledge of LPDDR4/5 protocol a definite plus o Ability to work independently and in small teams without close supervision required. Keywords: information technology Texas Design Verification Engineer [email protected] |
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| Fri Apr 12 18:55:00 UTC 2024 |