| Position: Font End Design Engineer at Austin, Texas, USA |
| Email: [email protected] |
| Position: F ont End Design Engineer Experience: 15+ Years Location: Austin, TX Semi-Conductor experience required, RTL Design and development, Must be local Hybrid role. Reporting to VP of Engineering Need only GC and USC.. 1099 also will work Type: 9 Month CTH w/ right technical and cultural fit JD: Experience with Verilog Strong Experience designing lots of CPU subsystems Experience w/ Arm based Micro Architecture (ARM or ARC) Familiarity w/ digital, analog design, and verification engineering Experience building world-class low-power MCUs targeting AI/ML-at-the-edge applications. Experience managing the design from architecture through tape-out and contributed by creating the design methodology, RTL design of multiple subsystem components, and resolving issues through physical implementation. RTL development (including architecture tradeoffs, testbenches, and synthesis) of a protocol engine to facilitate a next-generation Intel-based PC motherboard chipset interface Instituted methodology using Perl, HTML, and a database to track design metrics of area, performance, and power consumption. Optimization ( RTL-level) of several units within the GPU core with a focus on power reduction (global and local clock-gating, synthesis/timing closure, and power analysis). Hands-on development of Genus and Tempus scripts and coordination of backend activities using Innovis for floor planning / place / route. Engagement w/ external suppliers of IP and design tools. Execute timing and logic ECOs -- Keywords: artificial intelligence machine learning information technology green card Texas Position: Font End Design Engineer [email protected] |
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| Mon Apr 15 21:39:00 UTC 2024 |