| Job Opening :: Design Verification (Performance) Engineer :: Austin, TX (Hybrid) at Austin, Texas, USA |
| Email: [email protected] |
| From: Ben, Talent Junction [email protected] Reply to: [email protected] Hello, I hope youre doing Great..! My name is Ben (Technical Recruiter) and I am from Talent Junction LLC. I am reaching out to you about an exciting job opportunity with one of our clients. Talent Junction LLC is a highly recognized provider of professional IT Consulting Services across the USA. Should you have interest, please send a Microsoft word copy of your resume to [email protected] Please include the job title, authorization to work, interview/project availability, and contact information along with the details requested below. Remember, if you have the right set of aptitude and attitude, we have just the right job for youplease rush your resume now, we can guarantee immediate interviews. Job Title: Design Verification (Performance) Engineer Type: Contract Location: Austin, TX (Hybrid) JOB DESCRIPTION: Expectations include: The candidate is expected to develop in depth understanding of chip architecture and define/ develop performance verification scenarios to test design/ architecture and report bottlenecks/ optimization opportunities. The test cases should cover system scenarios/ benchmarks which stress target path/ feature as well as subsystem analysis. The reference metrics to qualify the results needs to be synthesized based on references from system architecture team, software team, IP team, industry standards or defined based on abstract use case descriptions available as part of design requirements. Strong skills in debug, failure re-creation and root cause analysis Work with peer teams to correlate performance metrics across different platforms (TLM, RTL, Emulation, Silicon validation, applications). Working with cross domains - IP owners, Systems and Core design teams to achieve performance verification objectives. Job Qualifications: Experience in below areas is needed. Experience with HDL/HVL like Verilog, System Verilog, VIP monitors, UVM methodology. Strong understanding Bus Protocols like AHB, AXI, NIC, ACE, NOC. Understanding of processor architecture, debug architecture, Cache Coherency Understanding of memory subsystems, caches, DDR controllers. Programming skills in C/C++/ Python or other languages. User experience to execute, analyze and debug test cases on emulation platform would be an added advantage. Domain knowledge in at least some of the areas like Graphics/Multimedia/Networking IPs like PCIe, MIPI, Ethernet, USB etc. System Verilog/UVM/Python/C/C++ Ben K Technical Recruiter Talent Junction 2060 Walsh Avenue, Suite 122, Santa Clara, CA 95050 E-mail Id : ben @talent-junction.com Hangout: | ben @talent-junction.com | Keywords: cprogramm cplusplus access management information technology California Idaho Texas Job Opening :: Design Verification (Performance) Engineer :: Austin, TX (Hybrid) [email protected] |
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| Fri May 03 01:05:00 UTC 2024 |