| FPGA Engineer !! Hybrid (mandatory 3 days in office) at Remote, Remote, USA |
| Email: [email protected] |
| Please share resume at [email protected] FPGA Engineer Caterpillar 1 Video to Hire MUST BS in Computer Engineering / Electrical Engineering 5-7 yrs industry experience with fpga design using HDL Will accept Master's or higher relevant internship/project experience toward minimum of 5 years required. Hybrid (mandatory 3 days in office) Real world FPGA experience is key requirement. Real world HDL and synthesis experience must be demonstrated on resume. Secondarily, experience with control software design patterns and anti-patterns, ANSI C, and other programming languages, version management tools, and software development processes such as Agile. Experience designing embedded electronics controls, display, or telematics software, including development of FPGA HDL & synthesis, device drivers, SPI/I2C peripheral interfacing, hardware diagnostics, operating system configurations, non-volatile memory interfacing, board initialization, and other chip-level interfacing. Thanks and Regards!! Akashika Pandey Technical Resource Specialist Ace Technologies Inc 2375 Zanker Road, Suite 250, San Jose, CA 95131 Phone: 408-442-3665 | Extn 4286 | Email ID/Hangout : [email protected] ------------------------------------------------------------------------------------------------------- Reporting Manager: Manish Sharma| Email ID : manish @acetechnologies.com | Phone: 408-442-3665 Ext 4298 Escalations : [email protected] Note: We respect your Online Privacy. This is not an unsolicited mail. Under Bills.1618 Title III passed by the 105th U.S. Congress this mail cannot be considered unsolicited as long as we include Contact information and a method to be removed from our mailing list. If you are not interested in receiving our e-mails then please reply with a "REMOVE" in the subject line to [email protected] and mention all the e-mail addresses to be removed with any e-mail addresses, which might be diverting the e-mails to you. We are sorry for the inconvenience -- Keywords: cprogramm information technology California Idaho FPGA Engineer !! Hybrid (mandatory 3 days in office) [email protected] |
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| Tue May 21 23:34:00 UTC 2024 |