Post Silicon Validation Engineer@Santa Clara, CA -onsite at Santa Clara, California, USA |
Email: [email protected] |
Hi Contract Role : Post Silicon Validation Engineer Location : Santa Clara, CA -onsite JD: Protocol: PCIE, Rthernet, JTAG, I2C Language: Python, C/C++, System Verilog Pre-silicon design verification & testbench Post-silicon validation on board & FPGA Testcase writing and Debug expertise & Silicon bringup Thanks & regards Acharya Sr. Lead IT Recruiter || TEL: 609-920-9222 Mail: [email protected] -- Keywords: cprogramm cplusplus information technology California Post Silicon Validation Engineer@Santa Clara, CA -onsite [email protected] |
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Wed May 29 19:21:00 UTC 2024 |