| Design Verification Engineer with pre-silicon design verification, C-shell scripting, Verilog-HDL & System Verilog, Cadence tools such as NCVerilog, NCSIM, Simvision Exp at Santa Clara, California, USA |
| Email: [email protected] |
| From: Sunil 3MKLLC, 3MK Software Solutions LLC [email protected] Reply to: [email protected] Hello, Greetings for the day!!! Please review the below roles and advise the best time to connect with you. If you are interested, you can reach me on Linkedin: linkedin.com/in/sunil-kumar-b-b42543302 and share resumes to [email protected] Hiring: Design Verification Engineer Onsite at Santa Clara, CA No Remote with pre-silicon design verification, C -shell scripting, Verilog-HDL & System Verilog, Cadence tools such as NCVerilog, NCSIM, Simvision Exp Work Location: Santa Clara, CA Duration: 6 Months Contract: Long Term Preferred Qualifications: 7+ years of experience in pre-silicon design verification Proficiency in C-shell scripting, Verilog-HDL & System Verilog. Strong knowledge in SV Assertions, UVM/OVM and functional code coverage. SOC Verification experience using ARM Cortex Microcontroller is required. Experience with advanced peripheral bus Verification IPs such as GPIO, UART, SPI, SW, JTAG, and I2C. Proficient with Cadence tools such as NCVerilog, NCSIM, Simvision. Experience with linting tools (i.e Spyglass) will be helpful. Exposure to SDF annotated simulations with good understanding of parasitic delays and timings is required. Exposure to FPGA programming and FPGA tools will be helpful. Independent, self-motivated with good analytical & communication skills. UVM/OVM/SystemVerilog/Python/C/C++ JOB DESCRIPTION : Responsibilities: Architect and Create verification environments using System-Verilog and Universal verification methodology-UVM IPs and SoCs with embedded CPUs and analog mixed-signal interfaces. Develop test plans and coverage metrics from specifications and writing block and chip-level tests. Create PERL/Python scripts to automate creating verification environments, tests generation and debugging. Failure analysis of Register Transfer Level and Gate simulations and resolve them by working with design engineers. Create low power testcases using UPF or CPF to verify the desired power intent of the SoC. Work with architects to determine the use-case scenarios to simulate Keywords: cprogramm cplusplus California Design Verification Engineer with pre-silicon design verification, C-shell scripting, Verilog-HDL & System Verilog, Cadence tools such as NCVerilog, NCSIM, Simvision Exp [email protected] |
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| Thu May 30 06:19:00 UTC 2024 |