| Title: DFT (Design-for-Testability) Engineer with JTAG interface, TAP controller architecture, Cadence tools for DFT Exp. at Remote, Remote, USA |
| Email: [email protected] |
| Hello Recruiters, Greetings of the day, This is Akash from, From Vensatek. I do have extraordinary specialized candidates on my bench who are looking for new C2C project roles. Please find the HOTLIST below and let me know if you have any C2C direct client positions with you Feel free to contact me Direct: 919-897-5679 E-Mail : [email protected] S.NoName of the ConsultantTechnologyYears of ExpVISAWork Location1KeerthanaUI Developer9+ YrsGCOnsite2Yaswanth Srinivas ChowdaryUI Developer9 YrsGCOnsite3Nikitha KothakondaUI Developer8+ YrsH4EADOnsite4Naveen MUI Full Stack Developer12 YrsH1BRemote/NC Hyb5MallaVarapu AvaneeshUI/UX8+ YrsH1BOnsite6Challa Naga phanindra ReddyJava Full Stack Developer8+ YrsGCOnsite7Pedda Kolimi RathanJava Full Stack Developer9 YrsGCOnsite8Ranga Sri VardhanJava Full Stack Developer7+ YrsGCOnsite9SravaniJava Full Stack Developer9 YrsGCOnsite10Rakesh VJava Full Stack Developer8+ YrsGCOnsite11Shravni BJava Full Stack Developer8+ YrsGCOnsite12Thumuganti SowmyaJava Full Stack Developer9 YrsH4EADOnsite13Nikhitha R.Net Developer8+ YrsH4EADOnsite14Ganga Bhavani.Net Developer9+ YrsH1BOnsite15Akhil.Net Developer9 YrsGCOnsite16K SwpanaSAS Programmer9 YrsH4EADOnsite17KeerthanaSAS Programmer9 YrsGCOnsite18SwapnaSQL DBA9+YrsGCOnsite19JayaPrakashSQL DBA8+YrsGCOnsite20Venkat SaiAEM Developer9 YrsGCOnsite21MadhulekhaAEM Developer8+ YrsH4EADOnsite22Aravind BandariData Engineer8+ YrsGCOnsite23Rakesk MData Engineer8+ YrsH1BOnsite24SwethaQA Automation engineer8 YearsH4EADOnsite25Mounika GAutomation engineer9+ YrsGCOnsite26Mohammed Firasat AliSr Test Lead/Quality Analyst9 YrsH1BOnsite27Mounika MQA Analyst8+ YrsH4EADOnsite28Dwarsala Jagadeeswar ReddyCyber Security8+ YrsOPT EADOnsite29SpandanaSr Cloud AWS Engineer8+ YrsGCOnsite30Shiva PrasadC++ Developer9+YrsGCOnsite31VishnuC++ Developer8 YearsGCOnsite32AnushaDevops Engineer9+YrsGCOnsite33Pramod UDevops Engineer9+YrsGCOnsite Thanks & Regards, Akash Bench Sales Recruiter akash.b @vensatek.com | 919-897-5679 13200 Metcalf Avenue, Overland Park, KS ,66213 On Fri, Jun 14, 2024 at 8:44PM <[email protected]> wrote: Hello, Greetings for the day!!! Please review the below roles and advise the best time to connect with you. If you are interested, you can reach me on Linkedin: www.linkedin.com/in/narayanarao2 and share resumes to [email protected] Title: DFT (Design-for-Testability) Engineer with JTAG interface , TAP controller architecture, Cadence tools for DFT Exp. Location: Santa Clara, CA (On-Site) Duration: 6+ Months Rate: Open / hr Following skillsets are must: - Experience with JTAG interface. - Experience with TAP controller architecture - Experience with Cadence tools for DFT - Experience with at speed vectors, Boundary scan, Compression mode etc. Job would require: - Stitching multiple scan chains across different IP(mixed signal) and clock domains. - Scan vectors generation, verification at different stages of the design. - Validating scan coverage across design. Job Description: 10+ years of hands-on experience with DFT and test flow with commercial EDA tools ( Synopsys, Mentor) for large and complex SoCs. Strong fundamental knowledge of DFT techniques include JTAG, ATPG, test pattern translation, yield learning, logic diagnosis, Scan compression, IEEE 1500 Std. and MBIST, LBIST. . Experience with Synopsys DFT Compiler, Tetramax and VCS is required. Experience with TestMaxDFT, SMS, TestMax Advisor tool suite is a plus. Experience in RTL simulation, synthesis, Linting, CDC checks, STA, DFT, quality metrics Hands-on expertise in writing System Verilog and VHDL Hands-on in Perl/TCL/Python/Unix scripting Excellent analytical, and problem-solving skills 8+ years industry experience, Masters degree or equivalent in EE or Computer Engineering (CE) Roles & Responsibilities Provide SoC (top) level constraints and partitions for RTL/Logic designers, floorplan & PD engineers, DFT requirements Perform top/block-level DFT insertion including scan compression, boundary scan, JTAG, IEEE 1500 wrapper, MBIST, LBIST, ATPG and pattern simulation. Verify DFT circuitry and interface with other blocks, debug timing simulation issues. Closely work with physical design team to generate and validate timing constraints. Be able to quickly understand problem statements and innovate solutions for DFT, diagnosis and yield learning. Be able to work independently and own the complete task from DFT specification to final pattern delivery for sub-system and/or SOC. Working closely with synthesis, STA, PD and DFT teams to meet all functional requirements, performance, power and area goals, functional and diagnostics test coverage Ability to lead/manage a team, with active technical interaction with engineering teams Education: BSEE, in Electrical/Computer) OR (MSEE, in (Electrical/Computer) Thanks & Regards, Narayana Rao Sr Manager (Recruitments) 3MK Software Solutions LLC Email: [email protected] Website: http://3mkllc.com/ Connect me on Linkedin too for daily updates and REQUIREMENTS: linkedin.com/in/narayanarao2 Note: WANT TO GET MY DIRECT CLIENT REQUIREMENTS DAILY Please click on below link and clink on Ask to join Group -- Keywords: rlang information technology container edition California Kansas North Carolina Title: DFT (Design-for-Testability) Engineer with JTAG interface, TAP controller architecture, Cadence tools for DFT Exp. [email protected] |
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| Fri Jun 14 20:56:00 UTC 2024 |