| System Screnario Stress (ARM Architecture)-Remote-Immediate Interview-HCL at Remote, Remote, USA |
| Email: [email protected] |
| From: Danish Azeez, Inherent technologies [email protected] Reply to: [email protected] Position: System Screnario Stress (ARM Architecture) Location: Remote Duration: 1 Years Phone & Skype Client: HCL Immediate Interview Need Details in below format only else will not consider the resume. LinkedIn Profile link , Education details, Contact number has to be on Resume : Candidate Name Contact No. Email ID Current Location Visa Rate Ex-HCL Candidate Details: iTAP BR# NA Candidate Reference No. NA Full Legal Name: First Name recorded in iTAP (Please share iTAP snippet) Middle Name recorded in iTAP (Please share iTAP snippet) Last Name recorded in iTAP(Please share iTAP snippet) Rate Consultant Location: Contact Number: Email ID: Interested to Relocate (Yes/NO): Highest Degree & Passing Year: Work Authorization (Must): Validity of Visa (If applicable): Availability for Onsite: Earliest Availability to Join: LinkedIn Profile: (Must) Current and Last few employers: Skill Rating Mandatory Skills Hands on experience in Years Last used -Year Self-Rating (Scale 1-10) 1. 2. 3. 4. Job Summary: We are seeking a highly skilled Verification Engineer with a minimum of 5 years of experience in the verification domain. The ideal candidate must have hands-on experience with System Verilog and UVM, and a solid understanding of the complete verification life cycle. The role requires expertise in SOC Integration and SOC verification, along with protocol experience in HBI, HBM, UCIe, PCIe, Ethernet, LPDDR5, and DFT. Key Responsibilities: Develop and execute verification plans, test benches, and test cases to ensure high-quality deliverables. Implement and utilize System Verilog and UVM for verification processes. Conduct thorough verification throughout the verification life cycle, from test plan creation to coverage closure. Perform SOC Integration and SOC verification, ensuring seamless protocol implementation and validation. Collaborate with design and development teams to identify and resolve verification issues. Analyze and debug test failures, identifying root causes and implementing corrective actions. Utilize protocol experience in HBI, HBM, UCIe, PCIe, Ethernet, LPDDR5, and DFT to ensure robust verification coverage. Maintain detailed documentation of verification processes, methodologies, and results. Keywords: Idaho System Screnario Stress (ARM Architecture)-Remote-Immediate Interview-HCL [email protected] |
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| Mon Jul 08 20:24:00 UTC 2024 |