| Looking for Design Verification Engineer (UVM , RTL) || Remote || 9+ Years at Mountain View, California, USA |
| Email: [email protected] |
| From: sharmi, SIF [email protected] Reply to: [email protected] Dear, Greetings from Smart IT Frame, Hope you are doing well!!! Smart IT Frame specializes in enabling you with your most critical line of resources. Whether its for permanent staffing, contract staffing, contract-to-hire or executive search, we understand the importance of delivering the most suitable talent; on time and within budget. With our Core focus in emerging technologies, we have provided global technology workforce solutions in North America, Canada & India. We take pride in delivering specialized talent, superior performance, and seamless execution to meet the challenging business needs of customers worldwide Role: Design Verification Engineer Location: Mountain View, CA Remote Contract Skills: UVM, Debugging Plan the verification of complex design IP/SoC like CPU/Core/GFX block. Develop tests using UVM. Identify and write functional coverage for stimulus and corner cases. Analyze and debug test failures with designers to deliver functionally correct design. Assembly tests for any ISA is strongly desired but not required. Close coverage to plug verification holes and meet tape out requirements. IP integration DV. Stimulus generation tools development and automation. Qualifications: Experience in design verification with a proven track record of delivering complex CPU or SoC IPs. In depth knowledge of verification principles, testbenches, stimulus generation and UVM based test environments. Solid understanding of computer architecture. Substantial background in debugging RTL (Verilog) designs. Good Knowledge of Scripting language such as Python. Keywords: information technology California Looking for Design Verification Engineer (UVM , RTL) || Remote || 9+ Years [email protected] |
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| Thu Jul 18 22:27:00 UTC 2024 |