| Very strong RTL-FPGA engineer at San Francisco, California, USA |
| Email: [email protected] |
| From: Eli, RCube Creative Consulting [email protected] Reply to: [email protected] Role : Very strong RTL/FPGA engineers with solid experience who can take Architecture/proposal to FPGA. Rate-DOE Location: San Francisco, CA Here is the JD Job description - Minimum 10+ years of experience in FPGA RTL development - Expertise in Architecture development, Micro-architecture specification and collaborate with stakeholders - Experienced with Programmable Logic EDA tools, such as AMD/Xilinx ISE/Vivado, Intel/Altera Quartus, - Should have worked in High configuration FPGA family series across many projects - Conversant in industry standard bus protocols [AMBA, PCI Express, DDR, ] - Demonstrable problem solving abilities. - Strong Experience in FPGA tool flows, Design bring-up, Synthesis and PNR - Development of timing constraints, analyse timing results, and implement design changes required to close timing - Should have ability to take ownership of issues and drive them to root cause and closure - Conversant in scripting languages for automation Xilinx + Arm Cortex 53 based expertise is preferable. Keywords: California Very strong RTL-FPGA engineer [email protected] |
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| Thu Jul 18 23:54:00 UTC 2024 |