| Senior ASIC.FPGA Verification Engineer---------Remote-------- Contract at Remote, Remote, USA |
| Email: [email protected] |
| From: Shekhar Bhadauria, TEK Inspirations LLC [email protected] Reply to: [email protected] Hi, We have an urgent opening with Senior ASIC/FPGA Verification Engineer and I have sent you job description, please go through it and let me know your comfort with it and also send me your updated resume ASAP Title: Senior ASIC/FPGA Verification Engineer Location: Remote Type: Contract Job Description: Strong UVM object-oriented test bench writing, System Verilog Must-haves UVM experience Highly skilled at object oriented programming Good functional coverage skills 5-12 years of experience High priority Experience with agile development and delivery Experience with git for revision control Excellent written and verbal communication skills BSEE or BSCS, or equivalent; MSEE preferred Candidate must able to qualify for DoD security clearance 10+ years of experience in a design engineering role focusing on functional verification 10+ years of ASIC/FPGA verification experience using SystemVerilog / UVM Must have experience in: Developing verification plans Designing and implementing SystemVerilog / UVM test benches for constrained-random verification Developing functional coverage models Writing and debugging directed and random test cases Enabling test benches for hardware acceleration Experience with automation/scripting (Perl, sed, awk, tcl/tk, sh) C programming desirable. SystemC and C++ used in conjunction with chip design and verification highly desired Good communication skills Experience with Formal verification / property checking is a plus Experience with emulation or FPGA prototyping is a plus RTL design experience and knowledge of standard protocols (such as PCIe) is a plus FPGA experience is a plus Keywords: cprogramm cplusplus information technology golang Senior ASIC.FPGA Verification Engineer---------Remote-------- Contract [email protected] |
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| Mon Jul 22 22:48:00 UTC 2024 |