| Design Verification Engineer | Bellevue, WA | Remote. at Bellevue, Washington, USA |
| Email: [email protected] |
| From: Shanmugapriya, vbeyond [email protected] Reply to: [email protected] Greetings from VBEYOND, I hope you are doing well. I am Shanmuga Priya S. from VBeyond Corp. We are a global recruitment company with a specialization in the hiring of IT professionals. One of our clients is looking for a Design Verification Engineer | Bellevue, WA | Remote. If you feel this requirement is not suitable for you, kindly share the same with your circle or reply REMOVE. Role : Design Verification Engineer Location : Bellevue, WA Mode : Remote Location: Remote Mandate : SoC , UVM . Plan the verification of complex design IP/SoC like CPU/Core/GFX block. Develop tests using UVM. Identify and write functional coverage for stimulus and corner cases. Analyze and debug test failures with designers to deliver functionally correct design. Assembly tests for any ISA is strongly desired but not required. Close coverage to plug verification holes and meet tape out requirements. IP integration DV. Stimulus generation tools development and automation. Qualifications: Experience in design verification with a proven track record of delivering complex CPU or SoC IPs. In depth knowledge of verification principles, testbenches, stimulus generation and UVM based test environments. Solid understanding of computer architecture. Substantial background in debugging RTL (Verilog) designs. Good Knowledge of Scripting language such as Python. Skills AZURE-INFRA-SERVICES Design Verification Engineer Bellevue, WA Remote Rate : $60-65 Location: Remote Plan the verification of complex design IP/SoC like CPU/Core/GFX block. Develop tests using UVM. Identify and write functional coverage for stimulus and corner cases. Analyze and debug test failures with designers to deliver functionally correct design. Assembly tests for any ISA is strongly desired but not required. Close coverage to plug verification holes and meet tape out requirements. IP integration DV. Stimulus generation tools development and automation. Qualifications: Experience in design verification with a proven track record of delivering complex CPU or SoC IPs. In depth knowledge of verification principles, testbenches, stimulus generation and UVM based test environments. Solid understanding of computer architecture. Substantial background in debugging RTL (Verilog) designs. Good Knowledge of Scripting language such as Python. Skills AZURE-INFRA-SERVICES Keywords: access management information technology Washington Design Verification Engineer | Bellevue, WA | Remote. [email protected] |
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| Tue Jul 23 19:54:00 UTC 2024 |