| Job Opening :: Design Verification Engineer :: Santa Clara, CA(Hybrid) at Santa Clara, California, USA |
| Email: [email protected] |
| From: Ben, Talent Junction [email protected] Reply to: [email protected] Hello, I hope youre doing Great..! My name is Ben (Technical Recruiter) and I am from Talent Junction LLC. I am reaching out to you about an exciting job opportunity with one of our clients. Talent Junction LLC is a highly recognized provider of professional IT Consulting Services across the USA. Should you have interest, please send a Microsoft word copy of your resume to [email protected] Please include the job title, authorization to work, interview/project availability, and contact information along with the details requested below. Remember, if you have the right set of aptitude and attitude, we have just the right job for youplease rush your resume now, we can guarantee immediate interviews. Job Title: Design Verification Engineer Type: Contract Location: Santa Clara, CA (Hybrid) JOB DESCRIPTION: Responsibilities: Architect and Create verification environments using System-Verilog and Universal verification methodology- UVM IPs and SoCs with embedded CPUs and analog mixed-signal interfaces. Develop test plans and coverage metrics from specifications and writing block and chip-level tests. Create PERL/Python scripts to automate creating verification environments, tests generation and debugging. Failure analysis of Register Transfer Level and Gate simulations and resolve them by working with design engineers. Create low power testcases using UPF or CPF to verify the desired power intent of the SoC. Work with architects to determine the use-case scenarios to simulate Preferred Qualifications: 7+ years of experience in pre-silicon design verification Proficiency in C-shell scripting, Verilog-HDL & System Verilog. Strong knowledge in SV Assertions, UVM/OVM and functional code coverage. SOC Verification experience using ARM Cortex Microcontroller is required. Experience with advanced peripheral bus Verification IPs such as GPIO, UART, SPI, SW, JTAG, and I2C. Proficient with Cadence tools such as NCVerilog, NCSIM, Simvision. Experience with linting tools (i.e Spyglass) will be helpful. Exposure to SDF annotated simulations with good understanding of parasitic delays and timings is required. Exposure to FPGA programming and FPGA tools will be helpful. Independent, self-motivated with good analytical & communication skills. UVM/OVM/SystemVerilog/Python/C/C++ Ben K Technical Recruiter Talent Junction 2060 Walsh Avenue, Suite 122, Santa Clara, CA 95050 E-mail Id : ben @talent-junction.com Hangout: | ben @talent-junction.com | Keywords: cprogramm cplusplus access management information technology California Idaho Job Opening :: Design Verification Engineer :: Santa Clara, CA(Hybrid) [email protected] |
| [email protected] View all |
| Mon Jul 29 18:45:00 UTC 2024 |