| Looking for Principal Verification Engineer at San Francisco, California, USA |
| Email: [email protected] |
| From: Likitha, GAC [email protected] Reply to: [email protected] Title: Principal Verification Engineer Location: San Francisco, CA, at least 1 day/week at Client site and rest of the week remote . Duration: 6 months Responsibilities: Architect and Create verification environments using System-Verilog and Universal verification methodology-UVM IPs and SoCs with embedded CPUs and analog mixed-signal interfaces. IP verification must have and SoC verification good to have. Develop test plans and coverage metrics from specifications and writing block and chip-level tests. Create PERL/Python scripts to automate creating verification environments, tests generation and debugging. Failure analysis of Register Transfer Level and Gate simulations and resolve them by working with design engineers. Work with architects to determine the use-case scenarios to simulate Preferred Qualifications: 7+ years of experience in pre-silicon design verification Proficiency in C-shell scripting, Verilog-HDL & System Verilog. Strong knowledge in SV Assertions, UVM/OVM and functional code coverage. Experience with advanced peripheral bus Verification IPs such as GPIO, UART, SPI, SW, JTAG, and I2C. Proficient with Cadence tools such as NC Verilog, NCSIM, Simvision. Experience with linting tools (i.e Spyglass) will be helpful. Independent, self-motivated with good analytical & communication skills. Keywords: cprogramm California North Carolina Looking for Principal Verification Engineer [email protected] |
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| Mon Aug 12 21:28:00 UTC 2024 |