| HCLTech || Urgent || ERS at Remote, Remote, USA |
| Email: [email protected] |
| Classification: Internal Hello Team We have received new VLSI requirements JDs I have added below , since the opportunities are urgent for now you can directly share the resumes over the email to us . all of these positions are Day 1 onsite. For any queries reach to me. STA Engineer San Jose. CA (Day1 Onsite) Buy rate: $75-$80/hr. C2C JD: 6 to 8+ years of hands-on experience in Static Timing analysis flows. Experience in Multi-mode/Multi-corner runs. Constraints development and management of multi partition design and top level Chip Level IO timing closure Experience in FUNC/DFT timing closure Experience in analysis of timing paths to identify key issues. Timing Convergence ( Both Inter/Intra block Level) Understanding of noise, cross-talk, OCV effects, margins, and constraints. Experience in timing and power ECO techniques and implementation Automation Skills using scripting languages like TCL/PERL/Python/SHELL Tools - Primetime/Tempus . Role: Physical Design (PnR) Location: Bay Area, CA (Day 1Onsite) Positions : 5 Client : Marvel Buy Rate: $70/hr. C2C JD: 5-10 Years Tape out experience in block level and full chip floorplan/full chip partitioning flow. Experience in independently analyzing/resolving congestion, timing issues and basic understanding of clock tree build Timing understanding to independently analyze timing paths Experience in 16/14nm or below flows. Experience in die-size estimation spread sheet IP based and synthesis based Experience in IO/Bump planning & placement, custom analog/PG planning and route implementation Equivalence check understanding. Good to have Conformal LEC experience Experience in ICC2/Innovus/DC tools Experience in RDL routing Experience in interfacing with cross functional teams and block PnR teams Good understanding of basic shell scripting, tool based TCL scripting to automate all custom activities Experience in version control systems Experience in managing/mentoring small teams .. Skill: RTL design / SoC integration Customer: Texas Instruments Location: Dallas, TX, USA (Onsite) Number of positions: 15 Start date: Immediate Duration: 6-12 months Buy Rate: $70-$75/hr. C2C JD: The candidate will work on a cutting edge ADAS processor SOC development. The candidate will be responsible for integrating complex third party IPs in the SOC. This includes configuration of the IP, developing required logic to integrate the IP into SOC, doing the RTL quality checks as needed/ fixing any Lint / CDC/ RDC issues, fix any defects reported by DV teams, work with Physical Design teams to address issues related to equivalence checks, timing closure, area optimization, etc. Ask the candidate to fill his expertise level for below interfaces / IPs. We will use it to screen the profiles. IP / Protocol Expertise Level: 1 (lowest) to 10 (highest) Remarks Gbit Ethernet PCIe Gen3 USB 3.0 CSI2 TX, CSI2 RX eDP (embedded display port) DSI (MIPI Display Serial Interface) DPI (Display parallel interface Thanks and Regards, Ankush Verma | Lead Recruiter Office: 732 485 0000 - 9086 Direct: 209-207-5752 Email: ankush@ cygnuspro.com Cygnus Professional Inc. https://www.linkedin.com/in/ankush-verma-7a1818b2/ Keywords: information technology California Texas HCLTech || Urgent || ERS [email protected] |
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| Thu Aug 22 20:13:00 UTC 2024 |