| Physical Design Engineer :: San Jose, CA (Onsite) :: Contract at San Jose, California, USA |
| Email: [email protected] |
| Hi, Hope you are doing great. My name is Devendra Pratap Singh and I am a Lead Talent Acquisition at Amaze Systems Inc.. I am reaching out to you on an exciting job opportunity with one of our clients. If you feel Interested then please share me your updated resume along with submission details. Title: Physical Design Engineer Location: San Jose, CA (Onsite) Type: Contract Only USC / GC Job Description: Physical Design Engineer, will play a crucial role in the RTL to GDS flow, including Synthesis and Place & Route (PNR). You will utilize tools such as Fusion Compiler and Cadence Innovus to optimize designs for performance, power, and area. Responsibilities will encompass macro placement, floor planning, clock tree synthesis (CTS), and routing. Key Responsibilities: Execute design planning tasks including partitioning, bump planning, and routing strategies. Lead and execute the full physical design cycle from RTL to GDSII for complex integrated circuits. Demonstrate proficiency in Static Timing Analysis (STA) to ensure design meets timing requirements. Utilize strong debugging skills to identify and resolve design issues efficiently. Integrate analog blocks into the digital design flow. Implement low power design techniques to optimize power consumption. Perform signoff checks including Logic Equivalence Checking (LEC) with Conformal, RTL Versus (RV) analysis with Ansys tools, Layout Versus (LV) with DRC clean-up utilizing Caliber, and Voltage Constraint Logic Planning (VCLP) with static checks. Drive timing closure through Physical ECO (Engineering Change Order) and Tweaker methodologies. Qualifications: Bachelor's or masters degree in electrical engineering or related field. 10-12 years of experience in physical design, with a strong understanding of RTL to GDS flow. Proficiency in Fusion Compiler, Cadence Innovus, and other relevant EDA tools. Thorough understanding of macro placement, floorplanning, CTS, and routing techniques. Experience with STA and timing closure methodologies. Knowledge of analog block integration and low power design principles. Familiarity with signoff checks including LEC, RV, LV, and VCLP. Excellent communication skills and ability to work effectively in a team environment. Skill Matrix: Skills Experience in Years RTL to GDS flow Fusion Compiler, Cadence Innovus, and other relevant EDA tools Macro placement, floorplanning, CTS, and routing techniques. STA and timing closure methodologies Analog block integration and low power design principles LEC, RV, LV, and VCLP. Devendra Pratap Singh | Talent Acquisition Specialist Amaze Systems Inc USA: 8951 Cypress Waters Blvd, Suite 160, Dallas, TX 75019 Canada: 55 York Street, Suite 401, Toronto, ON M5J 1R7 D: +1 ( 4 69) 424-3431 E: [email protected] | www.amaze-systems.com/ USA | Canada | UK | India Amaze Systems is an Equal Opportunity Employer (EOE), and does not discriminate based on age, gender, religion, disability, marital status, race and also adheres to laws relating to non-discrimination on the basis of national origin and citizenship status. -- Keywords: access management information technology green card California Texas Physical Design Engineer :: San Jose, CA (Onsite) :: Contract [email protected] |
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| Tue Aug 27 23:05:00 UTC 2024 |