| Urgent Requirement for :: DFX Engineer :: Austin, TX & Bay Area, CA at Austin, Texas, USA |
| Email: [email protected] |
| From: Romi, Appian Infotech Inc. [email protected] Reply to: [email protected] Job Title: DFX Engineer Location: Texas & California Create Verilog/System Verilog test benches to verify various DFT features in RTL such as SSN, compressed and uncompressed scan, memory BIST, JTAG, and boundary scan at block and SoC-level Verify top-level features such as power-on self-test, clock observation, clock stop and scan dump Run DV regressions & analyze coverage, triage & debug failures Experience in general design verification methodology, regressions, simulation and debug tools Expertise in Verilog or System-Verilog Working knowledge of scripting languages such as TCL, python (or another scripting language such as Perl) *If interested, revert back with your updated resume. Keywords: Urgent Requirement for :: DFX Engineer :: Austin, TX & Bay Area, CA [email protected] |
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| Tue Aug 27 23:11:00 UTC 2024 |