| Verification Engineer & SOC Verification in Bay Area, CA at Bay, Arkansas, USA |
| Email: [email protected] |
| From: Chandan Mishra, Appian Infotech [email protected] Reply to: [email protected] Job Title Verification Engineer Location: Bay Area, CA (Onsite) Duration: Contract Job Description: Expert on the System Verilog and Advanced knowledge of HVL methodology (UVM) Must setup up the verification environment, Test bench development, test plan and coding from scratch. Experience on any of the below protocols is added advantage: DDR/LPDDR PCIE Define ASIC/SoC verification strategy Full chip TB Architecture definition UVM based test bench development SV functional coverage, Assertions coding Test case development, coding, execution, bug analysis and end to end ownership. Experience in Perl/Shell scripting Should Co-ordinate with design team counterparts in RTL design. Job Title SOC Verification Location: Bay Area, CA (Onsite) Duration: Contract Job Description: 5+ years of experience with ASIC verification, SoCs or similar designs Experience working with Systemverilog and C/C++ based environments. Systemverilog and C/C++ language expertise Familiarity and experience with verification of PCIe protocol/designs Knowledge of AMBA Bus protocols APB/AHB/AXI Experience with Python and Tcl scripting languages Preferred: Experience with current emulation technologies - simulation acceleration, in-circuit emulation Thanks & Regards Chandan Mishra Team Lead - Recruitment Desk: 276-910-0155 Cell: 470-491-4178 [email protected] LinkedIn- https://www.linkedin.com/in/chandan-mishra-profile/ Website - www.appianinfotech.com Keywords: cprogramm cplusplus California Colorado Verification Engineer & SOC Verification in Bay Area, CA [email protected] |
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| Fri Aug 30 18:40:00 UTC 2024 |