| Urgent need of RTL design with IP PPA in Mountain View, CA at Mountain View, California, USA |
| Email: [email protected] |
| From: Chandan Mishra, Appian Infotech [email protected] Reply to: [email protected] Job Title RTL design with IP PPA Location: Mountain View, CA (Onsite) Duration: Contract The role involves providing customization spec to vendors and PPA comparison of different foundation IP (memories, std cells, GPIO, eFUSE) used in next gen consumer SOC products. It also extends to resolving foundation IP issues and enabling our design teams for execution. The candidate needs to: Work with arch, design & physical design teams to determine customizations for all foundation IP that are product differentiators Perform IP PPA analysis and vendor comparisons Provide specs and requirements to vendors Be able to understand and debug verilog, gls, dft, power management/upf modeling IP issues and communicate fixes to the team. Compile and create IP usage guidelines based on commonly encountered problems. Be data oriented, able to crunch through bug tracking system, and have front-end expertise Be able to multitask and respond quickly to different teams Profile Expectations: CS or EE/CE degree 5 years experience in semiconductor companies Minimum 2 years of experience with foundation IP development Preferred knowledge of std cell and memory design including tools and flows used for characterization, familiarity with lib template generation etc. Knowledge of RTL to GDS flow Scripting with preference on python knowledge Strong communication skills Ability to work independently Resourceful and solution driven individual Thanks & Regards Chandan Mishra Team Lead - Recruitment Desk: 276-910-0155 Cell: 470-491-4178 [email protected] LinkedIn- https://www.linkedin.com/in/chandan-mishra-profile/ Website - www.appianinfotech.com Keywords: information technology container edition California Urgent need of RTL design with IP PPA in Mountain View, CA [email protected] |
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| Fri Aug 30 19:40:00 UTC 2024 |