| Opening for Verification Engineer;Onsite Bay Area, CA or Austin, TX at Austin, Texas, USA |
| Email: [email protected] |
| From: Sajjad, RCI [email protected] Reply to: [email protected] Need Only LOCAL WITH Local DL Job Title: Verification Engineer ( Day1 Onsite) Location: Onsite Bay Area, CA or Austin, TX Duration: 6+ Months Contract End Client domain: Semiconductor industry Interview mode: Phone and Skype/Onsite ( Locals only) Visa: Any visa except OPT and CPT Experience level: 10+ years Requirement: Expert on the System Verilog and Advanced knowledge of HVL methodology (UVM) Must setup up the verification environment, Test bench development, test plan and coding from scratch. Experience on any of the below protocols is added advantage: DDR/LPDDR PCIE Define ASIC/SoC verification strategy Full chip TB Architecture definition UVM based test bench development SV functional coverage, Assertions coding Test case development, coding, execution, bug analysis and end to end ownership. Experience in Perl/Shell scripting Should Co-ordinate with design team counterparts in RTL design. Regards _______________________________ Sajjad Resource Consultings Services Inc. Parsippany, NJ Email: [email protected] linkedin.com/in/sajjad-husain-rana-b23588195 www.rconsultinginc.com Keywords: California Colorado New Jersey Texas Opening for Verification Engineer;Onsite Bay Area, CA or Austin, TX [email protected] |
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| Fri Sep 27 23:16:00 UTC 2024 |