| Urgent requirements for :: Design Verification Engineer :: Mountain View, CA at Mountain View, California, USA |
| Email: [email protected] |
| From: Nirbhay singh, Appian infotech Inc [email protected] Reply to: [email protected] Hi, We Have Urgent requirements for Design Verification Engineer Job Title: Sr. Design Verification Engineer Location: Mountain View, CA(onsite) Job Type: Long term Project Job Description: What You'll Be Doing: Strong PCIe expertise along-with complex SoC debug is must At-least 10+ years of experience in System Verilog HVL and C/C++. At-least 10+ years of experience in SV/UVM. Porting/Testing in FPGA & Emulation (Zebu) Hardware realization Platform is good to have Make/Perl/Python Ensure customer satisfaction. Reporting to customer on daily or weekly progress effectively What We Are Looking For: Experience in complete verification cycle which includes development of test plan, BFM/Driver/Monitor/Scoreboard component development and integration in test bench, stress/corner testing, failure debug, gate level simulations, assertions, and coverage closure. Verification closure with team Ensure customer satisfaction. Reporting to customer on daily or weekly progress effectively -- Regards Nirbhay Singh Sr. Talent Acquisition Specialist Appian Infotech Inc Direct No- 276 910 0146 Ext. 128 Office no-(Only for Text)- 276-284-3289 Email- [email protected] LinkedIn:- https://www.linkedin.com/in/n-k-singh-430076245/ Keywords: cprogramm cplusplus California Urgent requirements for :: Design Verification Engineer :: Mountain View, CA [email protected] |
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| Fri Oct 04 17:59:00 UTC 2024 |