| Need Senior Design Verification Enginee at Mountain View, California, USA |
| Email: [email protected] |
| From: Nikhil, CCIT INC [email protected] Reply to: [email protected] Job Title: Senior Design Verification Engineer Experience range - 10-15 years Location: Mountain View, CA 94043 (Day-1 Onsite) (5 days onsite) Key words/String : Verification AND PCIe AND Design AND SoC AND Verilog AND UVM AND (C/C++ OR Pearl OR Python) What You'll Be Doing: Strong PCIe expertise along-with complex SoC debug is must At-least 10+ years of experience in System Verilog HVL and C/C++. At-least 10+ year of experience in SV/UVM. Porting/Testing in FPGA & Emulation (Zebu) Hardware realization Platform is good to have Make/Perl/Python Ensure customer satisfaction. Reporting to customer on daily or weekly progress effectively What We Are Looking For: Experience in complete verification cycle which includes development of test plan, BFM/Driver/Monitor/Scoreboard component development and integration in test bench, stress/corner testing, failure debug, gate level simulations, assertions, and coverage closure. Verification closure with team Ensure customer satisfaction. Reporting to customer on daily or weekly progress effectively Thanks & Regards Nikhil Pathania [email protected] Keywords: cprogramm cplusplus California Need Senior Design Verification Enginee [email protected] |
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| Tue Oct 08 01:34:00 UTC 2024 |