| Urgent Requirement for :: Senior Design Verification Engineer :: Mountain View, CA at Mountain View, California, USA |
| Email: [email protected] |
| From: Romi, Appian Infotech Inc. [email protected] Reply to: [email protected] Job Title: Senior Design Verification Engineer Location: Mountain View, CA What You'll Be Doing: At-least 10+ years of experience in System Verilog HVL and C++. At-least 10+ years of experience in SV/UVM. Strong PCIe expertise is must Porting/Testing in FPGA & Emulation (Zebu) Hardware realization Platform is good to have Make/Perl/Python What We Are Looking For: Experience in complete verification cycle which includes development of test plan, BFM/Driver/Monitor/Scoreboard component development and integration in test bench, stress/corner testing, failure debug, gate level simulations, assertions, and coverage closure. Verification closure with team Ensure customer satisfaction. Reporting to customer on daily or weekly progress effectively Education: Bachelors / Masters Whats In It for You: We recognize that financial rewards and great benefits are important aspects of an ideal job. Thats why we offer competitive financial compensation, including various compensation plans and a solid benefits package. Medical, Dental, Vision Insurance 401k, With Matching Contributions Short-Term/Long-Term Disability Insurance Health Savings Account (HSA)/Health Reimbursement Account (HRA) Options Paid Time Off Tuition Reimbursement Growth Opportunities And more! *If interested, revert back with your updated resume. Keywords: cplusplus information technology California Urgent Requirement for :: Senior Design Verification Engineer :: Mountain View, CA [email protected] |
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| Tue Oct 08 02:59:00 UTC 2024 |