| Failure Analysis Engineer at Remote, Remote, USA |
| Email: [email protected] |
| From: Swati Nishad, Inherent Technologies [email protected] Reply to: [email protected] Position: Failure Analysis Engineer Location: San Jose, CA*Day 1 Onsite Duration: 1 Years Phone & Skype Client: HCL Immediate Interview Skill Rating Mandatory Skills Hands on experience in Years Last used -Year Self-Rating (Scale 1-10) 1. 2. 3. 4. Job Description As a Failure Analysis Engineer, you will be part of the quality and reliability group, performing failure analysis of ASIC products. Should have a passion for problem solving and a strong technical background in semiconductor failure analysis techniques and root cause analysis. This role will require high level of collaboration and interaction with Product Test Engineering, Design Engineering, Quality Engineering, Assembly Engineering and Foundry Engineering teams as necessary. Must be able to work well within a team and have excellent communication and organizational skills. Should have experience with a variety of semiconductor failure analysis test equipment and be able to interpret results and provide clear recommendations. Responsibilities Conduct Root cause analysis of reliability tests or field failures and propose corrective actions. Develop and implement standard processes for failure analysis. Coordinate all the logistics and instructions to direct the failure analysis process and carry out FA function in a systematic way. Document and report failure analysis results to management. Function as a technical resource for failure analysis questions. Develop and maintain relationships with vendors and suppliers. Requirements Bachelor's in Electrical/Electronics Engineering or related required. Master's Preferred 5+ years of experience in failure analysis field (preferably semiconductor). Semiconductor technology and process knowledge (Fab, Assembly, and Advanced Packaging). Experience of FA techniques like Cross sectioning, X-ray, CSAM, TDR, FIB, SEM, and TEM is required. Fundamental knowledge of fault isolation technique , ATE, Scan/ATPG debug preferred. Good understanding of transistor functions and basic electronics. Knowledge of JEDEC IC Qualification tests and requirements is beneficial. Innovative and Creative with troubleshooting techniques. Enjoy hands-on work and working in a lab environment. Good customer and vendor management skills. Ability to work well in cross-functional teams in a fast-paced, collaborative team environment. Ability to work independently, multi-task, and pay good attention to details. Keywords: California Failure Analysis Engineer [email protected] |
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| Wed Oct 09 20:21:00 UTC 2024 |