| Design Verification Engineer at Remote, Remote, USA |
| Email: [email protected] |
| From: Arbab Ahmed, TEK Inspirations [email protected] Reply to: [email protected] Hello, Hope you are doing well. I have an urgent requirement for Design Verification Engineer. I am sharing you the JD. Please have a look and let me know if you have any suitable candidate for this role. Job Description - Title - Design Verification Engineer Job Type - Remote Location: Sunnyvale, CA MOI - Skype Minimum Qualifications: Design Verification Engineering Services Testbench development System Verilog Universal Methodology (UVM), Python, and C tests Integration/development of C tests/Application Programming Interface (APIs) and software build flow Integration of UVM testbenches Test development and debug, including without limitation tests for functionality, power, performance, error, and connectivity, both for RTL and Gate Level Netlist Design Under Test, tests for functional and code coverage improvements Continuous integration and/or regression testing setup and debug for simulation at both RTL and Gate Level Netlist Unified Power Format (UPF) power aware simulation/emulation XProp simulation/regression TestBench creation and maintenance Coverage collection and closure Documentation of tests, testbench, use-cases, exclusions, and status Keywords: cprogramm access management California Design Verification Engineer [email protected] |
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| Wed Oct 16 18:37:00 UTC 2024 |