| Urgent need of Verification Engineer. at Dallas, Texas, USA |
| Email: [email protected] |
| From: Pavan Kuamr, WISEEQUATION SOLUTION INC. [email protected] Reply to: [email protected] Hi, I am Pavan Kumar and I work as a Sr. IT Technical Recruiter at Wise Equation Solution Inc . I saw your profile on the Job Board and I was really impressed by your experience. Position 1: Role: Design Verification Engineer Location: Dallas, TX (Onsite) Duration: Long Term Job Description : Minimum 7+ years of experience in Design Verification Strong experience in System Verilog, UVM. Experience with complex RAL configurations. Experience with full verification flow including coverage closure. Experience in High speed protocols like Ethernet / USB / PCIe / Infiniband. Position 2: Position-STA Engineer/lead Location- Austin,TX Duration: Long Term Role/ Responsibilities: Demonstrate a strong knowledge of all aspects of timing and synthesis for a wide variety of designs. Understand crosstalk, noise, OCV, timing margins. Familiarity with Clock specs, jitter, IR drop, spice analysis. Working with multi-site teams for execution Work with methodology teams to constantly improve flows and processes. BS/MS in Electrical or Computer Engineering 5-10+ years of experience in Static Timing Analysis Experience with STA Lead roles. Skills Required: Physical Design activities for MCU/MPU SoC's. Expertise in developing, implementing, and verifying STA constraints. Expertise in efficient closure of Subsystem as well as SoC-level timing including running optimization on PTECO for timing and Power. Knowledge of industry standards and practices in Timing closure, Physical Design, Floor-planning, and Place & Route Knowledge of basic Architecture and Verilog to collaborate with RTL and IP design teams for timing fixes. Contribute to timing flow and methodology improvements. Position: 3 Role: Verification Engineer Location: AustinTX/Sanata Clara,CA Duration: Long Term Requirement: Ideal Hands on experience of Jasper C2RTL Based in Austin or Santa Clara Otherwise Experience of sequential logical equivalence checking (SLEC) using other tools e.g. HECTOR from Synopsys Based in US who can visit Austin or ramp up Nice to have now through end of the year 2 engineers with preference for Austin Good experience of arithmetic data path verification Regards! Pavan Kumar Senior Technical Recruiter WISE EQUATION SOLUTION INC (Service-Disabled Veteran-Owned Company) Address: 3000 Polar lane Suite 903 Cedar Park TX 78613 Office No: +1 512 768 5201 Ext-216 Email: [email protected] Keywords: access management information technology microsoft California Texas Urgent need of Verification Engineer. [email protected] |
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| Fri Oct 25 02:15:00 UTC 2024 |