| Design Verification Engineer--Need local candidate at Remote, Remote, USA |
| Email: [email protected] |
| From: Abirami, Vdartinc [email protected] Reply to: [email protected] Hi, Please let me know your interest in below role. Role : Design Verification Engineer Location: Bay Area/Austin - Onsite Contract KEY RESPONSIBILITIES: Rich experience in constructing highly scalability, configurability, and reusability DV/Performance verification environment. Experience in ASIC design/verification related field in IP, Subsystem or SOC level Experience in writing System Verilog and/or System C models for simulation Working experience in writing UVM models, checkers, and stimulus, constructing UVM register models and applying constrained random methodology in UVM test environment and stimulus Compose test plan and validation vectors to ensure functional completeness Experience with design for verification (assertion-based design strategies, code coverage, functional coverage, test plan, gate-level simulation, back-annotation etc.) Versatile in any one of the high-level verification flows such as SV,UVM, C++ etc. as well as knowledge of industry standard tools for verification Excellent communication skills (both written and oral) Strong problem-solving skills Thanks & Regards, Abirami RA Lead Recruiter VDart Inc Phone : (470) 531-1739 Email ID: [email protected] Keywords: cprogramm cplusplus rlang Idaho Design Verification Engineer--Need local candidate [email protected] |
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| Wed Dec 04 00:20:00 UTC 2024 |