| Hiring! Design Verification Engineer in Bay Area (or) Austin - Onsite at Austin, Texas, USA |
| Email: [email protected] |
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Processing description: http://bit.ly/4ey8w48 https://jobs.nvoids.com/job_details.jsp?id=2055390&uid= From: Vijayakumar R, TechStar Group [email protected] Reply to: [email protected] Role: Design Verification Engineer Location: Bay Area/Austin - Onsite Hiring Mode: Contract Mandatory : Exprs AXI/AMBA KEY RESPONSIBILITIES: Rich experience in constructing highly scalability, configurability, and reusability DV/Performance verification environment. Experience in ASIC design/verification related field in IP, Subsystem or SOC level Experience in writing System Verilog and/or System C models for simulation Working experience in writing UVM models, checkers, and stimulus, constructing UVM register models and applying constrained random methodology in UVM test environment and stimulus Compose test plan and validation vectors to ensure functional completeness Experience with design for verification (assertion-based design strategies, code coverage, functional coverage, test plan, gate-level simulation, back-annotation etc.) Versatile in any one of the high-level verification flows such as SV,UVM, C++ etc. as well as knowledge of industry standard tools for verification Excellent communication skills (both written and oral) Strong problem-solving skills Keywords: cprogramm cplusplus rlang Hiring! Design Verification Engineer in Bay Area (or) Austin - Onsite [email protected] http://bit.ly/4ey8w48 https://jobs.nvoids.com/job_details.jsp?id=2055390&uid= |
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| 02:41 AM 07-Jan-25 |