| Hot C2C opening for Sr. Dynamic Memory Controller RTL Engineer - San Jose (or) Austin, TX (or) San Diego - Day 1 On-site at Austin, Texas, USA |
| Email: [email protected] |
| From: Gobi, PiplNow [email protected] Reply to: [email protected] Hi, Hope you are doing well. I have an urgent C2C opening for Sr. Dynamic Memory Controller RTL Engineer - San Jose (or) Austin, TX (or) San Diego - Day 1 On-site Our client is looking to fill this role immediately. Do share your updated resume, filled consultant details and filled Skill matrix asap. Skills Years of experience Over all Experience RTL design Memory controller Memory subsystem design RTL design experience on high performance and high efficiency digital designs JEDEC memory Bus protocols AMBA interconnect Cache subsystem design and optimization Consultant Details: Criteria Consultant's Data Full Name Primary Phone Primary Email Education (highest degree with major, year of graduation and name of institute) Active Certification Link LinkedIn Profile US work authorization and expiration Expected pay rate on C2C Current Company Name Current location (City/State) Willing to relocate (yes/No) Availability to join new project/ Notice period Have you ever worked or interviewed for this client in the past If yes, as a consultant or as an employee Last 5 digits of Social Security Number Birth month and day (NOT YEAR) Sr. Dynamic Memory Controller RTL Engineer Onsite San Jose (or) Austin, TX (or) San Diego Job Description As a senior RTL design engineer, you will work as part of a memory controller IP design team. You will be tasked with driving the RTL design, performance and power optimization of various sub-blocks of the dynamic memory controller. Solid engineer foundation and RTL design experience is desired for success. Key responsibilities include: Produce quality RTL on schedule meeting PPA goals Responsible for key blocks within the Memory Controller Engage with others for PPA optimization Partner with the physical design and CAD team to resolve implementation level details Work closely with design verification to test plan and otherwise ensure proper functionality Deliver quality micro-architectural level documentation Requirements Minimum requirements: BSEE, Computer Engineer or comparable and 7+ years of experience Experience owning and driving the RTL design of various sub-blocks of the memory controller for the high performance digital designs Demonstrated experience of successful Architectural through RTL design experience on high performance and high efficiency digital designs Detailed knowledge of memory subsystem design Detailed knowledge of existing and emerging JEDEC memory standards Preferred candidate will possess the following: Energetic, curiosity, and passion in logic design Good written and verbal communication skills Efficient digital design techniques Knowledge of interconnect and bus protocols with AMBA interconnect experience preferred Knowledge of cache subsystem design and optimization Keywords: Texas |
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| Tue Feb 07 02:47:00 UTC 2023 |