| HIRING || RTL design engineer || Bay Area, CA ||Day 1 Onsite|| Contract at Bay, Arkansas, USA |
| Email: [email protected] |
| From: Manish singh, Tanisha systems INC [email protected] Reply to: [email protected] Hi, Hope you are doing well, Let me know your interest in below position with updated resume & below mentioned details : Work Authorization : Current Location : Salary: LinkedIn ID : Contract/ Full time Job Title: RTL design engineer Location: Bay Area, CA (Day 1 Onsite) Experience level: 8-10 years Candidate Roles and Responsibilities Collaboration with offshore team. IC role and offshore task coordination Must have 10+ yr experience with ASIC design activities Verilog RTL, testcase debug, netlist checks, CDC checks, coverage analysis, timing closure, x-prop/gate level simulations. Preferred: Domain knowledge in PCIE/CXL, DDR, AMBA AXI/APB protocols. Please note: We strongly prefer the ASIC experience. If FPGA-only experience, then domain knowledge is must. Education: Bachelors Degree Regards, Manish Kumar Singh Tanisha Systems Inc. Office: 212-729-6543-Ext -616 | DIRECT 708-362-6477 Email: [email protected] LINKED IN - linkedin.com/in/manish-singh-47739816a Address: 99 Wood Ave South, Suite # 308, Iselin, NJ Keywords: California Idaho New Jersey |
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| Fri Feb 17 17:16:00 UTC 2023 |