| Hot C2C opening for Formal Verification Engineer Onsite at Austin, TX or San Jose, CA at Austin, Texas, USA |
| Email: [email protected] |
| From: Gobi, PiplNow [email protected] Reply to: [email protected] Hi, Hope you are doing well. I have an urgent C2C opening for Formal Verification Engineer Onsite at Austin, TX or San Jose, CA. Our client is looking to fill this role immediately. Do share your updated resume (by adding points about the below skills in the projects), filled skill matrix, filled consultant details, Visa and DL copy asap. Skill Matrix: Skills Years of Experience Overall Experience CPU and/or GPU design Python, Perl, or TCL VC Formal or Jasper Gold RTL design memory subsystem design Consultant Details: Criteria Consultant's Data Full Name Primary Phone Primary Email Education Certifications (if any) LinkedIn Profile US work authorization and expiration Expected pay rate/hr on C2C Current Company Name Current location (City/State) Willing to relocate (yes/No) Availability to join new project/ Notice period Have you ever worked or interviewed for this client in the past If yes, as a consultant or as an employee Last 5 digits of Social Security Number Birth month and day (NOT YEAR) Formal Verification Engineer Local to Austin or San Jose 12+ months contract Job Description Technical Description As a Formal Verification Engineer you will contribute to the design of GPU IP. This is a hands on role, driving next generation product development with a high level of contribution and knowledge base needs. Key responsibilities include: Review architecture specifications Identify key design features for formal verification Develop formal verification plans Work with RTL to create formal verification-friendly reference models Manage tasks and deliverables to meet milestones Drive formal verification closure Requirements Preferred candidate will possess the following: Deep understanding of CPU and/or GPU design Proficiency in scripting languages such as Python, Perl, or TCL Experience with formal tools such as VC Formal or Jasper Gold Strong capability to read high level design specification and RTL to create/execute verification plans BSEE, Computer Engineer or comparable and 7+ years of experience Experience owning and driving the RTL design of various sub-blocks of the memory controller for the high performance digital designs Demonstrated experience of successful Architectural through RTL design experience on high performance and high efficiency digital designs , System Verilog skills can read and understand designs and test benches Detailed knowledge of memory subsystem design Detailed knowledge of existing and emerging JEDEC memory standards Preferred candidate will possess the following: Energetic, curiosity, and passion in logic design Good written and verbal communication skills Efficient digital design techniques Knowledge of interconnect and bus protocols with AMBA interconnect experience preferred Knowledge of cache subsystem design and optimization Thanks & Regards Gobinath. B Vice President - Client Success | PiplNow, LLC Keywords: California Texas |
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| Tue Mar 14 17:00:00 UTC 2023 |