| Urgent Requirement || RTL Design Engineer || Mountainview, CA(Local) || c2c at Mountain View, California, USA |
| Email: [email protected] |
| Job Title: RTL Design Engineer Location: Mountain View, CA Experience level: 8+ Years Roles and Responsibilities: 7+ years of related technical engineering experience 5+ years of experience applying digital design principles in SoC and/or IP development. Proficient in Verilog/System Verilog coding constructs. Knowledge of front-end tools (Verilog simulators, Connectivity tools, CDC checkers, low power static checkers, linting) Experience with high speed PCIe designs and protocols. Experience with Industry standard interface protocols such as AXI, APB, etc. Experience with ARM Fabric IPs. Experience with IPXACT. Understanding of Computer Architecture fundamentals. Ability to write scripts using Python, Tcl, Perl etc. Experience in EDA tools such as VCS, VCLP, Spyglass Lint, Questa CDC, Fusion Compiler, Design Compiler, Genus Proficiency with UPF (Low power intent) Proficiency in clock crossing techniques. Knowledge of Static Timing Analysis and understanding of timing signoff fundamentals. Mandatory Skills: Candidate should be good in RTL Design, high speed PCIe designs and protocols, Industry standard interface protocols such as AXI, APB, etc. Position 1: Design background in Arteris NoC (Network on Chip) RTL generation or based on any other NoC tool Position 2: Fabrics on chip, fabric design, Microarchitecture Position 3: Front-end checks, Protocols: PCIe, AMBA/AXI, RTL Education: Bachelors/Masters degree in engineering Thanks and Regards, Sapna Verma ( Technical Recruiter ) 1603, Capitol Ave, Suite 310 A461, Cheyenne Wyoming 82001 Email : [email protected] LinkedIn I'D : linkedin.com/in/sapna-verma-aa172a246 -- Keywords: information technology California |
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| Mon Jul 17 19:13:00 UTC 2023 |