| Design verification Engineer at Austin, Texas, USA |
| Email: [email protected] |
| From: Benjamin Thomas, Concord it systems .INC [email protected] Reply to: [email protected] Design verification Engineer Duration: 6 Months Contract Location: Austin, TX and Bay Area, CA (Remote okay) Client : Wipro Area of expertise: System Verilog, UVM, Ethernet Good experience with Processor Sub-system & System level verification (10+ years for lead & 5+ years for Team members) building a testbench for a medium complexity block using System Verilog and UVM Writing random tests, directed tests, error tests & performance tests for a sub-system of medium complexity using System Verilog and UVM. Developing, maintaining and supporting of the UVM verification environment. Debugging tests with design engineers to deliver functionally correct design blocks OOPS, randomization, constraints, interfaces writing & analyzing functional coverage, assertions Generating and analyzing code coverage & writing waivers Knowledge on Palladium for emulation is a plus Keywords: information technology California Texas |
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| Wed Aug 02 23:54:00 UTC 2023 |